Getting Started with RISC-V

RISC-V is an exciting new open source processor design which will be of particular interest to developers of custom IP. This short overview will help you understand RISC-V,  its eco system, and the opportunities it presents.

RISC-V Foundation

Technical Overview

  • Wikipedia has a good technical overview, including a list of open-source implementations which could be useful for bootstraping a project instead of starting from scratch with the low-level instruction set specification (the “ISA”). https://en.wikipedia.org/wiki/RISC-V

Some RISC-V Users

  • Google’s OpenTitan project seeks to provide an open-source silicon root of trust (RoT) using a RISC-V-based RoT design with integration guidelines for use in data center servers, storage devices and peripherals. https://opentitan.org/
  • Kneron is a California-based company known for its impressive line of AI SoCs. Kneron’s KL530 targets the autonomous vehicle edge computing market specifically. In addition to a RISC-V AI-coprocessor, the chip also includes a neural processing unit, a Cortex M4 core for system control, an image signal processor, and a dedicated security block. https://www.allaboutcircuits.com/news/knerons-risc-v-ai-chip-intends-to-bring-level-1-and-level-2-autonomy-to-any-vehicle
  • Western Digital is moving its consumption of IP cores (1B per year!) to RISC-V, as well as offering commercial RISC-V IP. https://www.westerndigital.com/en-ca/solutions/business/risc-v
  • SiFive provides three families of RISK-V IP, covering high-performance application processors, area-optimized, low-power embedded 64- and 32-bit microcontrollers, as well as vector processors. https://www.sifive.com/blog/risc-v-chiplets-disaggregated-die-and-tiles
  • Apple posted in September for a “RISC-V High Performance Programmer” to work in their Vector and Numerics Group (which is responsible for “designing, enhancing and improving various embedded subsystems running on iOS, macOS, watchOS and tvOS.”). Candidates should be experienced with RISC-V architectures, and ideally have a working knowledge of NEON micro architecture in ARM CPU cores. https://appleinsider.com/articles/21/09/03/apple-investigating-risc-v-processor-architecture-job-listing-shows

Mentions in Popular Media

Examples of Development Boards

Software Development

 

Please let me know in the comments section if you have found this overview useful,

 

Performance Monitoring using htop

htop is a great tool for viewing the basics of what a server is doing, in particular the real-time CPU and memory graphics. However, the colors in the bar graphs can make it difficult to distinguish between CPU tasks being executed (low-priority, normal, kernel and virtualiz), and the type of memory in use (used, buffers and cache). 

In this case, the “no-color” option can be used which causes the bar graphs to use characters instead of colors for sub-categories.

% htop -C

Exploring Server Performance

I recently rebuilt the server for dalescott.net after a drive failure. When complete, it seemed ERPNext wasn’t as snappy as before.

My final conclusion was, at the time, the server was likely being subjected to a penetration attack. The server commonly has spikes of 1K+ penetration attempts in a 24hr period, which tend to occur sporatically in clusters. However reivewing server performance was still a useful exercise.

dalescott.net SaaS Architecture

The host server is a Intel Core2 CPU 6600 2.40GHz with 6GB of RAM. The VirtualBox vm running ERPNext is a single-core with 2GB RAM (essentially taking one core and 2GB from the host).

Load At Rest

Below is the virtual machine and host server when at rest (no logged-in ERPNext users, and no on-going brute-force ssh or web app login attempts). The vm load (top) is 3% and the host (bottom) server cores are 5% and 2% (the 2% core is the erpnext server).

Load When Stressed

Below is the server when an ERPNext user logs in and accesses an Item list. The vm load (top) has maxed out at 100% and is using half its available memory. On the host (bottom), core #2 is almost 70% (erpnext), but core #1 is only 35% and only half the total available memory is being used, which is good.

Conclusion

Clearly ERPNext is processor-constrained in this situation, but at least under normal server load is still very suitable for either presentations or training with a limited number of concurrent users.